About Us

Through consulting, training, and contracting services, Correct Designs integrates leading edge methodologies with EDA and client tools to enable overall solutions while increasing engineering productivity. To learn more about Correct Designs, read more below or contact us.

Steve Burchfiel

Founder and President

Steve Burchfiel is the co-founder and president of Correct Designs, Inc. Steve focuses on business operations and technical leadership for Correct Designs training and software products. He is also an active consultant, specializing in the application of simulation-based testbench methodologies and advanced verification languages.

Recently, Steve has led, and assisted with, the development of a new set of comprehensive hardware design, verification and modeling courses offered by Correct Designs. He has also assisted clients with the development, deployment, training and support of Vera and SystemVerilog base class libraries for use world-wide. Steve has taught hundreds of students around the world how to use advanced verification methodologies and base class libraries using professional quality, multi-day courses developed by Correct Designs. Steve also has extensive experience developing reusable verification intellectual property (VIP) and VIP reuse standards.

Prior to his recent work at Correct Designs, Steve was the co-founder and president of Severity1 Incorporated, an EDA company specializing in advanced Verification planning software. Severity1 software was used by multiple Fortune 100 semiconductor companies for developing reusable, coverage driven verification plans. Severity1 was sold to a large EDA company in 2006. Steve oversaw business operations and was very involved with the product requirements, development, sales, marketing, training and product deployment.

Prior to Correct Designs and Severity1, Steve was a senior partner and project leader at Silicon Resources, an Austin based consulting and software company. Steve also managed a large verification team at IBM and provided technical leadership on the design and verification of POWERPC, x86 and System390 CPUs.

Steve received his Bachelor of Science degree from the Institute of Technology at the University of Minnesota.


Kevin Schott

Cofounder and Executive VP

Kevin has over 25 years of experience in logic verification of high-performance processor designs and simulation methodology development, including several years of management. In addition to being Vice President of Correct Designs, most recently Kevin has provided expert instruction, teaching SystemVerilog to verification and design engineers all over North America. He has developed the core training materials for a 1-week course in the SystemVerilog design and verification language.

In parallel Kevin taught the e language and e Reuse Methodology to hundreds of engineers worldwide as a certified Specman instructor. He developed all the training material for the Specman Elite 5-day class being used worldwide by a major EDA vendor.

After leading 3 years of product development for Severity1 (another company that Kevin co-founded in 2003), he sold software licenses for that product to Fortune 100 semiconductor companies. This software technology enabled verification engineers to automate the verification planning process. This technology was acquired by a major EDA vendor in 2006, through which Kevin led product enhancements, and supported its transfer to the new company.

In 2003, as part of the IBM, Toshiba, Sony partnership team developing “Cell” (a high-performance gaming processor used by Sony and others), he led a verification team to define and execute a system verification plan to simulate the Cell processor with 2 complex I/O chips. While personally writing thousands of lines of e code as a hands-on technical contributor, he led an international multi-site, multi-company development team (who were new to Specman) to execute a detailed test plan.

In 2000, while consulting at Agere, he wrote thousands of lines of e code as the simulation lead on a 10Gbit network processor classifier chip using self-checking, directed-random simulation methodology. He’s developed test plans, correctness models, test cases, and perl code to produce a high quality simulation environment being used by dozens of his client’s design and verification engineers.


After receiving a BSEE in 1983 from Tulane University in New Orleans, Kevin joined IBM and helped bring into production, a research-prototype simulation accelerator in Boca Raton, FL. In 1984, he supported the IBM DSL/1 logic design language, simulator, and synthesis tools. In 1986 he was technical lead on developing an 8-port communications adapter for the 9370 systems. Kevin was asked to manage a department of engineers developing PS/2 memory and communications adapters in 1988. After moving to Austin in 1990, Kevin staffed and managed large verification departments including the team working on the Power2 RISC chipset used in IBM workstations. He was asked to lead the verification of the 615 processor on assignment in Burlington, VT for one year in 1995. Upon his return to Austin, he led the verification teams for the 630 Power3 design, and the GigaProcessor Power4, the most complex processor developed by IBM. In 2000 before leaving IBM, he was one of only 3 verification engineers ever to reach the level of Senior Technical Staff Member in the company at that time.


Will Mitchell

Cofounder and Executive VP

Will, Vice President and co-founder, manages business operations at Correct Designs including, finances, contracts, employee placement & recruiting. However, at his core Will is an engineer first and foremost with a passion for providing services to our many clients. Will is a career verification engineer with decades of experience verifying some of the industry’s most complex designs including: sever class microprocessors, memory subsystems, network processors, gaming chips, DSPs, network hubs, medical devices and assorted other digital logic.

Due to his in-depth understanding of all aspects of the verification process, from planning through closure, Will is regularly tapped by our clients to lead the development and execution of the verification process. These tasks have included everything from educating and leading team members, to the development of verification plans, verification environments, simulation tools and simulation infrastructure.

Will is an expert object oriented programmer and software/testbench architect, having developed millions of lines of software. Over the years Will has used System Verilog/UVM, Specman/e, SystemC, C++, perl and other scripting languages in his verification tasks. As one of Correct Designs primary technical instructors Will has taught thousands of engineers on topics such as Advanced Verification Methodology, Specman/e, SystemC and C++.

Prior to founding Correct Designs with his partners in 2000 Will spent over a decade at IBM where he led the development of verification environments, verification tools & simulation infrastructure for Power and x86 processors. Will is a graduate of the University of Massachusetts with BS degrees in Electrical Engineering and Computer Systems Engineering. An avid, hiker, backpacker and skier Will lives in Vermont with his wife, two sons and dog.


Cadence Connections Verification Program

Siemens Questa Vanguard Program