Training

Correct Designs delivers the best design and verification training in the industry, provides superior quality, and places high attention to the details. Our material, developed and delivered by recognized industry experts, uses real world examples leaving the students with the ability to be immediately productive.

Our courses provide practical knowledge that design engineers can immediately apply. We focus on application rather than theory, history, and academic nuances. Our content includes methodology topics that are required to leverage advanced languages & libraries and our instructors are uniquely-qualified to deliver this subject matter. Click here for course listings.

Quality

We use a rigorous internal development process with checklists to ensure quality. Code snippets used on our slides are tested, employing proprietary Visual Basic automation to ensure quality. Our labs are ensured for simulator portability and tool version compatibility.

Instructors

Our instructors are senior engineers who worked on very large projects, for companies that are industry leaders in design and verification. All have over 20 years of industry experience, and continue to consult on leading edge products and methodologies. They all have prior training experience with superior class scores, having taught several hundreds of students.

Differentiators

We have a lean business model where much of our material was developed in partnership with large companies, and are unrestricted by a particular tool vendor implementation. We maintain partnerships with the major EDA vendors, and our material is developed by practicing experts in the field of study, not academics, or merely full-time trainers.

Courses

SystemVerilog Class (with UVM Intro)

This course provides the student with practical instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language, SVA and UVM for verification. The course demonstrates the benefits of the language and library features, and how to make verification more efficient and effective using SystemVerilog, SVA and UVM.

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SystemVerilog Assertions In-depth

This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog Assertion constructs. The course demonstrates the benefits of using SystemVerilog Assertions, and how to make designs more efficient and effective using SVA constructs.

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SystemVerilog for RTL Designers

This SystemVerilog course provides the RTL design engineer with recommendations and guidelines for the most useful SystemVerilog constructs and their effect on synthesis. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.

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SystemVerilog Fundamentals with SVA

This SystemVerilog course provides the student with an in-depth introduction to learning and applying the most useful constructs and concepts provided by the SystemVerilog language. The course demonstrates the benefits of the language features, and how to make designs more efficient and effective using SystemVerilog constructs.

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Verification Using SystemVerilog

This SystemVerilog course provides the student with in-depth instruction for learning and applying the most useful constructs and concepts provided by the SystemVerilog language for verification.  The course demonstrates the benefits of the language features, and how to make verification more efficient and effective using SystemVerilog constructs.

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